There is an increasing demand in data processing applications for nonvolatile memory storage. Random access memory cells typically store a data state as either a charge on a small capacitor or as the condition of a bi-stable circuit. However, neither of the storage techniques retain the stored data state when power for the memory cell is removed.
A number of forms of MOS memory have been developed in the effort by the prior art to obtain true nonvolatility in semiconductor random access memory (sometimes referred to as RAM) cells. One class of prior art efforts has accomplished this through the coupling of a RAM with some type of nonvolatile memory. The nonvolatile counterpart serves as a one to one mapping of the volatile RAM, and can be loaded with the contents of the RAM when desired, as, for example, just prior to a power loss. This approach has an additional benefit in that it is possible to store two independent data sets simultaneously, one in volatile form and the other in nonvolatile form, with neither disturbing the other, during the normal RAM access operation. As a result, a fixed data set can be recalled from the nonvolatile memory through non-volatile recall as desired. Thus, for example, it is possible to call a fixed data set to initialize a particular data base.
The static RAM cell has generally taken the form of a cross-coupled latch (flip-flop) while the nonvolatile memory has consisted of various Electrically Erasable and Programmable Read Only Memories (EEPROM). These prior art efforts are described, for example, in U.S. Pat. No. 4,103,185, issued July 25, 1978; U.S. Pat. No. 4,103,348, issued July 25, 1978; and U.S. Pat. No. 4,128,773, issued Dec. 5, 1978. The last-listed patent discloses the use of a variable threshold transistor which can store charge on an insulated gate element to change the threshold voltage of the transistor in a nonvolatile logic latch circuit. The charge stored can be maintained for an extended period of time without external power, which provides the nonvolatile data storage. In addition, the prior art is described in an article by Harari et al at page 108 of the 1978 ISSCC Digest and in an article by R. Klein et al at page 111 of the Oct. 11, 1979 issue of Electronics. The Harari et al article describes a thin oxide floating gate EEPROM cell configuration which accomplishes nonvolatile transformation through Fowler-Nordheim (F-N) tunneling.
These prior art approaches, however, suffer from three principal deficiencies. First, the data stored in these prior art nonvolatile systems are in the inverse state rather than in the true state. This complicates the control of the memory since additional steps are required to convert the stored data from the inverse to the true state. Moreover, since this must be carried out each time data is recalled, the speed of operation of the memory is substantially reduced. The further complexity of working with the inverse rather than with the true state of the data can also require that additional circuit elements be used in the memory, thus increasing the cost and size of the overall memory array. Second, when a prior art nonvolatile circuit has been incorporated within the hold-down element of the flip-flop, as described in the Harari et al article, excessive shifts in threshold voltage arising from the presence of the nonvolatile state can degrade or inhibit volatile cell operation. Consequently, undesirable and costly tight design and operating margins are required. Third, while a number of approaches have been described to circumvent the necessity for tight design and operating margins, as for example, the system described in the above-noted U.S. Pat. No. 4,128,773, the solution is generally at the expense of larger memory cell size. This prior art solution fails to obviate the cost problem and may create operating speed problems.
In view of these deficiencies in the prior art, there exists a need for a nonvolatile random access memory cell which can store the true state of data for an extended period of time, provide a fast read of stored data, require a minimum number of operation controls, not be a critical component of the volatile RAM cell, and utilize a minimum number of circuit elements.